The present invention relates to a delta-sigma (ΔΣ) A/D converter, especially, to a delta-sigma A/D converter provided with plural channels for converting an analog input signal into a digital signal.
Various arts on a delta-sigma A/D converter have been proposed up to now. For example, Patent Document 1 describes an art which can control zeros in the quantization noise shape with a high degree of accuracy, and without the necessity of considering the minimum size of a process in use. Patent Document 2 describes an art which suppresses an adverse influence of an idle tone generated in a delta-sigma A/D converter, with the use of a direct-current (DC) dither signal (DC addition voltage). Here, an idle tone is a periodic noise signal caused by an integrating circuit and a feedback loop of the delta-sigma A/D converter, when there is no analog input signal to the delta-sigma A/D converter, or when the analog input signal concerned is very small. Details of the idle tone are described in Non-patent Document 1, for example.    (Patent Document 1) Japanese Patent Laid-open No. Hei 6 (1994)-120837    (Patent Document 2) Japanese Patent Laid-open No. 2003-163596    (Non-patent Document 1) “Understanding Delta-Sigma Data Converters”: authored by Richard Schreier and Gabor C. Temes, Japanese translation edition supervised by Takao Waho and Akira Yasuda (Literal translation of the title of Japanese edition is “An introduction to delta-sigma analog-to-digital converter”), published by Maruzen Co., Ltd., October 10, Heisei 19 (2007), pp. 34-37.